A DMOS transistor is a MOS field effect transistor in which a source layer and a body layer to be a channel are formed by double diffusion, and is used as a power semiconductor device for a power supply circuit, a driver circuit, etc.
In recent years, there is a need to decrease the on-resistance of a DMOS transistor for a demand for smaller electronics and lower power consumption. Therefore, pitches between transistors are decreased by using a micro-fabrication technique so as to increase the number of transistors per unit area. Furthermore, lower on-resistance is realized by decreasing the channel length of a transistor by forming a body layer by an oblique ion implantation technique instead of by thermal diffusion that has been employed conventionally.
Hereafter, a structure of an N channel type lateral DMOS transistor and a method of manufacturing the same will be described referring to FIGS. 12 and 13. FIG. 12 is a plan view showing a pattern of a lateral DMOS transistor, and FIG. 13 is cross-sectional views of FIG. 12, in which FIG. 13(A) is a cross-sectional view of FIG. 12 along line X-X and FIG. 13(B) is a cross-sectional view of FIG. 12 along line Y-Y.
An N type source layer 11 is formed in the front surface of an N type semiconductor substrate 10 (e.g. a silicon single crystal substrate). The source layer 11 is made of an N type layer 11A and an N+ type layer 11B of which the concentration is higher than that of the N type layer 11A.
Furthermore, a gate insulation film 12 and an insulation film 13 for electric field reduction (a LOCOS film) connected to the gate insulation film 12 are formed next to the source layer 11 on the front surface of the semiconductor substrate 10, and a gate electrode 14 (e.g. made of a polysilicon film) is formed from on this gate insulation film 12 onto a portion of the insulation film 13 for electric field reduction. This gate electrode 14 is formed so as to surround the source layer 11 like a ring, and the source layer 11 is exposed from the tetragonal opening of the ring-like gate electrode 14. Furthermore, a spacer film 15 (e.g. made of a silicon oxide film) is formed on the sidewall of the gate electrode 14, and the high concentration N+ type layer 11B of the source layer 11 is formed by using this spacer film 15.
Furthermore, an N+ type drain layer 16 is formed in the front surface of the semiconductor substrate 10. The drain layer 16 is disposed apart from the source layer 11, and the insulation film 13 for electric field reduction is disposed between these.
Furthermore, a P type body layer 17 is formed so as to be partially superposed on the source layer 11 and extend in the front surface of the semiconductor substrate 10 under the gate electrode 14. When a voltage applied to the gate electrode 14 is a threshold voltage or more, the front surface of this body layer 17 is inverted to N type to form a conductive channel between the source layer 11 and the drain layer 16.
Hereafter, a method of forming the body layer 17 will be described. A photoresist layer 18 is formed so as to have ends on the gate electrode 14 and cover the insulation film 13 for electric field reduction and the drain layer 16.
The source layer 11 and an end of the gate electrode 14 abutting the source layer 11 are exposed from the photoresist layer 18. Oblique ion implantation of P-type impurities is performed in four directions shown by allows A, B, C and D in FIG. 12. In detail, ion beams are applied to the front surface of the semiconductor substrate 10 in oblique directions relative to the vertical direction by using the gate electrode 14 and the photoresist layer 18 as a mask.
This oblique ion implantation realizes the formation of the body layer 17 in a narrow region under the gate electrode 14, thereby decreasing the channel length of the transistor and achieving lower on-resistance.
A DMOS transistor is described in Japanese Patent Application publication Nos. hei 10-233508 and 2004-039773, for example.